1. Field of the Invention
The present invention relates generally to dynamic semiconductor memory devices having a small area occupied thereby and more particularly, to a semiconductor memory device comprising two-transistor type memory cells.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a conventional three-transistor type memory cell used in an FIFO (first in first out) memory from which data first inputted thereto is first read out, or the like.
The memory cell comprises a data storing transistor 1, a data writing transistor 2, a data reading transistor 3 and storage capacitance 4. An n channel MOS field effect transistor is used as the transistors 1, 2 and 3. In the memory cell, information "1" and "0" are represented depending on presence/absence of charges in the storage capacitance 4. The data storing transistor 1 has its gate connected to a write data bit line 5 through a source and a drain of the data writing transistor 2. The data writing transistor 2 has its gate connected to a write selecting line 6. The data writing transistor 2 serves as a write gate. In addition, the data storing transistor 1 has its source connected to a read data bit line 7 through a source and a drain of the data reading transistor 3. The data reading transistor 3 has its gate connected to a read selecting line 8. The data reading transistor 3 serves as a read gate.
Description is now made on an operation of the memory cell. The read data bit line 7 is generally precharged to a positive potential V.sub.PR. The write selecting line 6 and the read selecting line 8 are generally held at a zero potential. At the time of a write operation, the write selecting line 6 is held at the positive potential and the read selecting line 8 is held at the zero potential. It is assumed that information "1" is written. In this case, if the write data bit line 5 is held at a predetermined positive potential, the potential is transmitted to the data storing transistor 1 through the data writing transistor 2, so that the storage capacitance 4 is charged.
In addition, it is assumed that information "0" is written. In this case, if a write data bit line 5 is held at a zero potential, the zero potential is transmitted to the data storing transistor 1 through the data writing transistor 2, so that the storage capacitance 4 is discharged.
Thereafter, the write selecting line 6 is returned to the zero potential, so that the information "1" or "0" is held in a memory cell 9. Since the storage capacitance 4 is discharged or charged due to a leakage current such as a subthreshold current of the data writing transistor 2 so that the information gradually disappears, the storage capacitance 4 must be refreshed or data must be read out within a constant time period.
At the time of a read operation, the read selecting line 8 is held at the positive potential and the write selecting line 6 is held at the zero potential. If and when information "1" is stored in the memory cell 9 so that the storage capacitance 4 is charged to the positive potential, the read data bit line 7 which is precharged in advance to the positive potential V.sub.PR is discharged to the zero potential through the data reading transistor 3 and the data storing transistor 1. On the other hand, if information "0" is stored in the memory cell 9 so that a potential of the storage capacitance 4 is the zero potential, the data storing transistor 1 is rendered non-conductive, so that the read data bit line 7 remains at the precharge potential V.sub.PR. Thus, information stored in the memory cell 9 can be known by examining the potential on the read data bit line 7.
FIG. 2 illustrates an example of a circuit for precharging the read data bit line 7 and a sense amplifier circuit for amplifying the potential on the read data bit line 7.
When a precharging signal PC applied to a gate of a precharging transistor 101 rises to an "H" level, the transistor 101 is rendered conductive, so that the read data bit line 7 is precharged to a power-supply potential V.sub.CC. When information is read out to the read data bit line 7 from the memory cell, an output of an inverter 102 attains the "H" or "L" level depending on the potential on the read data bit line 7. When a sense enable signal SE applied to a gate of a transistor 103 rises to the "H"level, the output of the inverter 102 is held in a latch circuit comprising inverters 104 and 105.
A semiconductor memory device using three-transistor type memory cells is described in, for example, "Introduction to nMOS and CMOS VLSI System Design", pp. 268-273.
Since a memory cell included in the conventional semiconductor memory device is structured as described above, four devices (3Tr, 1C) are required for every memory cell. Consequently, the cell size is increased, which is not suitable for increasing capacity of the semiconductor memory device.
Furthermore, in the FIFO memory employing the above describe memory cell, data can be transferred only in one direction, so that two FIFO memories must be employed when data is transferred in both directions among a plurality of systems.